This application is based upon-and claims the benefit of priority from the prior Japanese Patent Application No. 11-046389, filed Feb. 24, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device having a transistor structure in which a punch-through stopper layer is formed mainly within a semiconductor substrate so as to lower the impurity concentration in the channel region and a method of manufacturing the same.
In order to improve the performance of a semiconductor device having a MOS structure, it is very important to achieve a high performance of the MOS transistor. The high performance of the MOS transistor represents, for example, (1) increase in the driving current, (2) reduction in the nonuniformity of the threshold voltage, and (3) reduction in parasitic resistance/parasitic capacitance. The increase in the driving capability has been achieved by shortening the gate length (or channel length). However, if the channel is shortened, the threshold voltage Vth is lowered by punch-through, leading to an increase in a so-called xe2x80x9cshort channel effectxe2x80x9d that the threshold voltage cannot be controlled by the gate electrode.
In order to suppress the short-channel effect, efforts have been made to make the thickness of the gate insulating film as thin as possible and to increase the impurity concentration in the channel region to about 108 cmxe2x88x923. However, it is impossible to decrease the thickness of the gate oxide film beyond the maximum electric field because of the restriction imposed by the maximum allowable electric field Emax capable of guaranteeing the reliability. Also, if the impurity concentration in the channel region is made unduly high, the impurity of the high concentration in the channel region is scattered so as to saturate the drain current, with the result that the drain current is not increased even if the channel is shortened. Further, the miniaturization of the device is accompanied by an increase in the resistance of the gate electrode and by generation of parasitic resistance in the source-drain regions.
For overcoming these problems, it has been proposed to decrease the impurity concentration in the channel region formed on a punch-through stopper layer having a high impurity concentration, to use a salicide structure in the source-drain regions, and to use a metal electrode. These measures have been individually put to a practical use.
For example, known is a structure that, after element isolation such as LOCOS, a high impurity concentration layer is formed by ion implantation in the channel region for stopping the punch-through, followed by forming a thin epitaxial silicon layer about 10 nm thick, which is not doped with an impurity, on the channel stopper region so as to form a MOS transistor having a channel region of a low impurity concentration, as disclosed in xe2x80x9cIEDM Technical Digest pp.433-436 (1993) (T-Ohguro et al.)xe2x80x9d or xe2x80x9cIEEE Transactions on Electron Devices, Vol. 45, No. 3 (March 1998), pp. 710-716 (T. Ohguro et al.)xe2x80x9d.
FIGS. 1A, 1B and 1C are an upper view, a cross sectional view in a channel length direction, and a cross sectional view in a channel width direction, respectively, collectively showing the conventional semiconductor device. As shown in FIG. 1B, an element separating insulating film 201 is formed on a silicon substrate 101. A punch-through stopper layer 102 doped with a high concentration of an impurity is formed within the silicon substrate 101. An epitaxial silicon layer 103 is formed on the surface of the silicon substrate 101. A gate electrode 107 is formed on the epitaxial silicon layer 103 with a gate insulating film 106 interposed therebetween. Further, source-drain regions 108 are formed apart from each other in the epitaxial silicon layer 103 and the silicon substrate 101 except the region below the gate electrode 107.
In manufacturing a semiconductor device having the particular transistor structure, the element isolating insulating film 201 is formed first in the silicon substrate 101, followed by forming the epitaxial silicon layer 103 on the substrate 101 at about 600xc2x0 C. It should be noted that the epitaxial silicon layer 103 is formed after formation of the element isolating insulating film 201. Therefore, it is possible for the epitaxial silicon layer 103 poor in crystallinity to be formed in edge portions of the element isolating region. The epitaxial silicon layer 103 is formed in region A shown in FIG. 1 along the width of the channel. However, the problem of current leakage tends to take place in region A.
Another method is conceivable for avoiding the current leakage problem. Specifically, the punch-through stopper layer 102 having a high impurity concentration is formed first on the silicon substrate 101, followed by forming the epitaxial silicon layer 103 and subsequently forming the element isolating insulating film 201. However, since a heat treatment step under a high temperature is employed in the element isolating step, a problem is generated that impurities are diffused again from the punch-through stopper layer 102 having a high impurity concentration into a region having a low impurity concentration.
To be more specific, formation of the low impurity concentration layer in the channel surface region is made difficult by various high temperature processes including the high temperature process for forming an interfacial oxide film or densifying the buried oxide film in the element isolation step, the high temperature process for forming the gate oxide film and after-oxidation process, the high temperature process for activating the source-drain regions, and the high temperature process for silicidation of the source-drain regions.
As described above, where an element isolation is performed first, followed by forming an epitaxial silicon layer in the conventional semiconductor device, the epitaxial silicon layer poor in crystallinity extends to overlap with the edge portion of the element isolating region, leading to leak current generation. By contraries, where the epitaxial layer is formed first, followed by performing the element separation, formation of a low impurity concentration layer in the channel surface region is made difficult by the high temperature processes for forming the interfacial oxide film for element separation, which is performed after the epitaxial silicon layer formation, for densifying the element isolating insulating film, for forming a thin gate oxide film, and for activating the source-drain regions.
An object of the present invention is to provide a semiconductor device having a transistor structure that makes it possible to suppress the short channel effect accompanying the miniaturization of the transistor and to suppress the current leakage.
Another object of the present invention is to provide a method of manufacturing a semiconductor device having a transistor structure that makes it possible to suppress the short channel effect accompanying the miniaturization of the transistor and to suppress the current leakage.
According to a first aspect of the present invention, there is provided a semiconductor device, comprising a transistor structure including an epitaxial semiconductor layer of a first conductivity type formed on a main surface of a semiconductor substrate of the first conductivity type, a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in at least the epitaxial semiconductor layer, a channel region of the first conductivity type formed between the source region and the drain region, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein the channel region in the interface with the gate insulating film has an impurity concentration lower than that of the semiconductor substrate, and the source region and the drain region do not extend to overlap with an edge portion of the element isolating region.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming a high impurity concentration layer of a first conductivity type in at least a part of a semiconductor substrate of the first conductivity type;
forming a semiconductor layer of the first conductivity type by an epitaxial growth method on a main surface of the semiconductor substrate;
selectively removing the epitaxial semiconductor layer and the semiconductor substrate to form a trench, followed by burying an insulating film for element isolation in the trench; and
forming a transistor in a region where the insulating film for element isolation is not formed.
Further, according to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming a high impurity concentration layer of a first conductivity type in at least a part of a semiconductor substrate of the first conductivity type;
forming a semiconductor layer of the first conductivity type by an epitaxial growth method on a main surface of the semiconductor substrate;
selectively removing the epitaxial semiconductor layer and the semiconductor substrate to form a trench, followed by burying an insulating film for element isolation in the trench;
selectively forming a gate insulating film and a gate electrode on the epitaxial semiconductor layer; and
forming a source region of a second conductivity type and a drain region of the second conductivity type with the gate electrode used as a mask,
wherein the steps after formation of the high impurity concentration layer are carried out under temperatures not higher than 700xc2x0 C.
The MOS transistor in the present invention is constructed such that an epitaxial semiconductor layer poor in crystallinity does not extend to overlap with an edge portion of the element isolating region so as to suppress the current leakage. Also, the gate electrode is of a laminate structure consisting of a polycrystalline silicon (polysilicon) film doped with an impurity and a silicide film or a metal film formed on the polysilicon film. The particular construction is effective for decreasing the resistance of the gate electrode. What should also be noted is that the impurity concentration in the channel region in the vicinity of the interface with the gate insulating film is set lower than that in the substrate, making it possible to prevent the drain current from being lowered while suppressing the short channel effect.
Among the total process of forming a MOS transistor, the steps after formation of a layer having a high impurity concentration can be carried out at low temperatures lower than 700xc2x0 C., making it possible to form a channel region having a low impurity concentration and a layer having a high impurity concentration below the channel region. To be more specific, by suppressing the impurity diffusion from the layer having a high impurity concentration into the channel region in the step of forming the channel region, the impurity concentration in the channel region in the vicinity of the interface with the gate insulating film can be maintained at a level lower than that in the semiconductor substrate. Also, the presence of the layer having a high impurity concentration below the channel region serves to suppress the short channel effect. The impurity diffusion from a layer having a high impurity concentration into the channel region can be prevented by manufacturing a semiconductor device at process temperatures not higher than 700xc2x0 C., as described in xe2x80x9cIEDM Technical Digest pp. 433-436 (1993) (T-Ohguro et al.)xe2x80x9d or xe2x80x9cIEEE Transactions on Electron Devices, Vol. 45, No. 3 (March 1998), pp. 710-716 (T. Ohguro et al.)xe2x80x9d.
Further, the element separating insulating film is formed after formation of the channel region by epitaxial growth in the present invention, making it possible to overcome the difficulty inherent in the process in which the element separating insulating film is formed first, i.e., the difficulty that a semiconductor layer poor in crystallinity is formed to extend to overlap with the edge portion of the element separating insulating film.
An additional feature of the present invention is that the depth of each of the source region and the drain region is prevented from being increased by using the low temperature process, making it possible to control the effective channel length Leff and to achieve a transistor structure adapted for suppressing the short channel effect.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.